Vitis is Xilinx’s unified software platform, replete with open source libraries optimized for Xilinx’s own hardware platforms and pre-built applications. The Genesys ZU is our “kitchen sink” development board boasting oodles of peripherals and connectors powered by a Xilinx UltraScale+ 3EG MPSoC. It would only make sense to take something big and powerful and make it faster, right?
We talked Adam Taylor of Adiuvo Engineering into creating such a demonstration for us. OpenCL is an open source framework from the Khronous Group designed for heterogeneous systems, and at its core is the concept of “Host” and “Kernel”. When designing systems using a heterogeneous SoC (like in our Genesyz ZU), it’s possible to accelerate algorithms from the processor to programmable logic using OpenCL for development of the processing system (Host) and programmable logic (kernel).
To get started developing using the Vitis OpenCL acceleration flow on the Genesys ZU you first need to create a base Genesys ZU Vitis platform. Secondly, you must configure PetaLinux targeting the ZU. Then, the Vitis platform needs to be created and the project run.
Adam runs through this process in great detail on his Hackster Project titled “Genesys ZU Vitis Acceleration Platform“.