Not to long ago, I wrote a post about what a state machine is. That post covered the state machine as a concept and way to organize your thoughts. Well, if you are looking to use state machines in FPGA design, the idea isn’t much help without knowing how to code it.
As you know from the last post, a state machine is made up of three components. The next state logic, state register and output logic.
The first component I’ll go through is the next state logic. This is coded directly from the state diagram.
I’m going to put the state diagram here for reference.