A point of confusion for a lot of people new to FPGA design is the constraints file. People are used to just writing code and having it work. However, in FPGA design we have to specify what hardware is being used.
The part that is easiest to grasp for most users is the .v or .vhd file, depending on if you are writing in Verilog or VHDL. This is where you write what you want to do. So, say you want to implement a simple AND gate. You want the inputs to be switches, and the output to be an LED. In Verilog you would write:
Assign LED = SW0 & SW1;
This would AND together SW0 and SW1, and assign LED that value. In computer science, at this point you would be done. Your variable LED has its value.
However, in hardware language, you need to connect that “Net” to a physical component, or its pin location. The same needs to be done for the switches. This is done in the constraints file.
The way I like to think of a constraints file is like magical stairs from Harry Potter:
The base of the staircase is like the net. You know where that leads to, but the stairs have the ability to go anywhere (any physical pin location), and until they are connected they don’t lead anywhere. Well, the constraints file is like the stairs connecting. Once the constraints file is written, the pin location is set, you know the bottom of the stairs is connected to LED and you know the top is connected to say H17. However, just like the stairs you can easily change the final destination, by changing the pin location.
When using Xilinx tools, which is what is used with Digilent boards, you have two types of constraints files, UCF (user constraints files), and XDC files (xilinx constraints files), to be used with ISE and Vivado, respectively.
Each of these types of constraints files contains the same information. For all the pins it contains a net name, a pin location, and the IO signaling standards. The net name, is like a variable name. It’s what you want that pin to connect to in your design. The pin location is the physical pin that you want to send the signal to. The IOStandard is like a communication protocol.
This is the basic information a constraints file requires, but it can also contain more information.
So say I want to connect pin H17, which is led 0 on the Nexys 4, to my output LED, with iostandard LVCMOS33.
For a UCF file I would need to write:
NET “LED” LOC=H17 | IOSTANDARD=LVCMOS33;
For an XDC file I would need to write:
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED }];
Luckily, you don’t have to type this whole thing out from scratch for everything you want to use on the FPGA. You can download the master UCF or XDC file from the product page of the FPGA you are using, uncomment the lines you need, and change the net name to match your design.
So, to finish my example, in the design I would need:
#.v file
module AND (
input SW0,
input SW1,
output LED
);
assign LED = SW0 & SW1;
endmodule
And for the constraints file either:
# UCF
NET “SW0” LOC=J15 | IOSTANDARD=LVCMOS33;
NET “SW1” LOC=L16 | IOSTANDARD=LVCMOS33;
NET “LED” LOC=H17 | IOSTANDARD=LVCMOS33;
Or:
#XDC
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW0 }];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW1 }];
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED }];
The XDC and UCF file I used in this example is on the Nexys 4 DDR product page. To view a XDC or UCF file in action see any of our many FPGA examples on the Wiki.
