Imagination University Program and Xilinx University Program will host two one-day workshops designed specifically for teachers on May 13th and 14th. It is based on the soon-to-be released “MIPSfpga” core. The workshop will be held at Harvey Mudd College, Claremont, Southern California, USA. MIPSfpga is a configuration of the MIPS microAptiv family found in many embedded devices.
With its long heritage and excellent documentation, MIPS is the preferred choice of RISC architecture for many teachers around the world. But to demonstrate key concepts in the past, teachers had to settle for creating partial “MIPS-like” cores or using unofficial copies of dubious heritage.
This workshop will show the audience how to use “MIPSfpga” core as part of a computer arrchitecture course, which will pave the way for students to use this core in their projects, effectively creating their own system on chip (SoC) designs. The attendee can dissect MIPS RISC processor (MIPSfpga) RTL in depth using the Digilent Nexys 4 DDR. After the training, attendees will be aware of its potential to revolutionize the teaching of Computer Architecture.
All delegates will be given access to the MIPSfpga core, the full Getting Started Guide (written by Sarah Harris with contributions from Parimal Patel), detailed reference documentation about MIPS microAptiv, and other vital information/programs that enable the whole package to work effectively.
Here is the workshop information. The details can be found at Imagination Community.
Educators can register here.
- Prof. Sarah Harris, University of Nevada at Las Vegas. Co-Author of “Digital Design & Computer Architecture” by Harris & Harris.
- Dr. Parimal Patel, Principal Trainer and Content Developer for the Xilinx University Program (“XUP”).
- Munir Hasan & Sachin Sundar, Solutions Engineers at Imagination Technologies.
- Welcome & Introduction to the Imagination University Programme (“IUP”)
- Introduction to MIPSfpga
- Software Installations: Codescape MIPS SDK & Vivado
- Simulation: Increment LEDs program.
- Nexys 4 DDR board: Increment LEDs delay program
- Nexys 4 DDR board: Synthesizing core
- Codescape MIPS SDK: using Codescape to develop and debug C and assembly code
- Bus Blaster/OpenOCD: using the Bus Blaster JTAG probe and OpenOCD to debug a target system
- Lab 1: Writing C code – reaction timer
- Lab 2: Adding 7-segment display I/O and modifying memory amounts
- Integrating Xilinx IP blocks with MIPSfpga
- Porting to other boards – Example: Basys3
- Teaching Materials in Development for MIPSfpga / Wrap-up / Q&A
Be the first to get hands-on experience with a non-obfuscated, fully verified MIPS core for teaching and projects!