PAL vs. CPLD vs. FPGA

At the heart of all digital logic are the basic primitives of the AND and OR gates. To assist in the design of large complex digital designs, companies developed integrated circuits (ICs) to pack as much logic as possible into a small size. The important devices that came out of this development were the PAL, CPLD, and FPGA.

PALs

The first widely used device from this development was the Programmable Array Logic (PAL) device. PALs are made using two building blocks: A logic plane and output logic cells. PALs generally have around 20 I/O pins, a relatively small amount compared to newer devices yet vastly superior to working with multiple 7400 series ICs to achieve the same result.

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The next generation of programmable logic was the complex programmable logic device (CPLD). The main advantage of a CPLD over a PAL is the larger number of available gates and I/O pins. This allows for large, high-speed logic designs in a small package. A typical use case for a CPLD is to configure an FPGA upon boot. The NetFPGA-SUME uses a CPLD for this purpose. CPLDs have non-volatile memory and maintain configuration, even after a reboot. This is unlike a FPGA, which loads a configuration from an external memory device. If you are interested in CPLD development check out the CoolRunner-II CPLD Starter Board or the Original Cmod.

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Field Programmable Gate Arrays (FPGAs) are completely reconfigurable devices that have gate counts in the millions and hundreds of I/O pins. This allows for highly complex designs, such as processors, to be created and tested. Since they are very configurable, development costs are greatly reduced compared to the alternative of designing an Application Specific IC (ASIC). Also notable is the relative simplicity of fixing bugs in the logic design. If a bug is found in post-production the FPGA configuration memory can be easily updated. See our selection of FPGA development boards in the store.

 

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