The Digital Discovery was very recently announced and made available for purchase. I was able to get my paws on one of the first units that arrived into the warehouse and was eager to get it up and running.
Knowing that this product was almost ready, I spent some time working on a simple, all-digital project that could highlight some of the Digital Discovery’s capabilities. Using the bread-board compatible, 48-pin CMOD A7 FPGA board, I modified a project sourced from the Digital Design textbook. The project simply counts from 0-9999 and then resets back to 0. The digits are all displayed on a 7-segment LED display.
Since the CMOD A7 has no on-board 7-segment display like many of it’s older and bigger brothers, I needed to add the external analog driver circuit to the board. This made for some interesting coding artifacts, like both anode and cathode pins are driven to the same logic level because I have a BJT between the FPGA pin and the LED that inverts the logic level. But it worked like a charm.
Once I had the code and driver all working correctly, I needed to add the Digital Discovery to the mix. The Digital Discovery has 40 I/O pins, 24 of which are dedicated as high-speed inputs connected to the front 32-pin port. Two additional PMOD compatible ports are located on either side of the device and can be used for both input and output.
I needed to monitor 11 pins total, 1 for each segment and 1 for each cathode, so I used the fly-wire harness on the 32-pin connector and connected pins 0-10 to the A7.
Once I had it all connected, it was just a simple matter of recording the data using the WaveForms software.
Here’s the data zoomed in.
The A7 is a great board for simple projects and was chosen specifically because it doesn’t have the on-board 7-segment LED display. But the system clock only goes up to 12 MHz. The Digital Discovery defaults to 200 million samples per second (MS/s), but is capable of up to 800 MS/s, which would be way beyond the reach of the A7 clock to try and max it out. The Nexys 4, however, has a 100 MHz system clock. That sounds promising, so let’s see what that looks like.
In order to use the 800 MS/s option, you have to use the High-Speed Adapter…
…and the included High-Speed Probes.
The probes connect to the HSA by connecting the black side to the GND rail and the red side to the input port.
The signals were routed in code to PMOD connectors JA and JB, where the probes were also attached. The GND pins were tied together using a small bread-board power supply rail. The free ends of the probes come with heat-shrink tubing attached to give some strength to the connection, but it makes it difficult to place more than 3 wires next to each other on a standard bread-board with 100 mil spacing. Hence the need to get a little creative with the connections.
The code was then modified to work with the Nexys 4 board and then loaded. The Ones digit on the 4-digit display was driven by the 100 MHz system clock. The Thousands digit was therefore cycling 0-9 at 10 kHz. In short, way, waaay, wwwaaaaayyyyyy too fast for the human eye to see.
By making a couple of adjustments to the Digital Discovery Logic Analyzer controls…
…and then recording the data…
… we can start to see the data. In the above image, the chunk of data to the left of the first red cursor is the segment signal data while the Thousands digit is turned on. Zooming in on the cursor we get the following:
We can clearly see the segment signals coming through and represented by the decimal values at the top of the bus in blue. Remember that we are looking at 7-segment coded values, so a binary value of “1111000”, when mapped to the segments “GFEDCBA” and noting that the signal is active low, tells us that segments A, B, and C are on and we get the decimal digit “7” on the display. Looking through the rest of the decimal data we see that we are counting 0-9 and then resetting back to 0, all in 100 μs. Perfect.
Now let’s zoom in on that big white block of data to the right. That’s the data coming in to the display when the Ones digit is selected, clocked at 100 MHz.
I added a bunch of cursors to highlight the timing intervals. The cursors are all 10 ns apart, and when you look at the decimal value displayed in the blue line at the top at each cursor, it matches the same sequence of data as the image seen before. Once again, we are cycling through the digits 0-9 and resetting back to 0, but this time each digit is ticking at 100 MHz. Between each cursor, we have 8 data points, which is why there are no sharply defined transitions between states. It may seem like there is some errant data recorded, but note that when the data on the blue line seems to be noisy, we have several channels in that bus all changing states at the same time. It seems like these signals are not all changing at the same time. But let’s consider something. The copper traces on the Nexys 4 PCB that connect the FPGA chip to the PMOD headers were not designed to be distance matched, meaning that at this time scale, the physical distance between the PMOD headers and the FPGA has introduced a propagation delay in the signal that we cannot avoid. But we can see this introduced delay in the recorded data above. I don’t know about you, but I thought that was actually quite fascinating to be able to see that, especially on a device as small and compact as the Digital Discovery.
For the full project, including some high resolution images of the recorded data and the project code details, check out my Instructable. Also, be sure to check out the Digital Discovery reference page for a getting started guide, WaveForms tool tutorials, reference manual, and community projects.