On June 2nd in Los Angeles, USA at ISCA 2018, and June 24th in Salt Lake City, USA at ASEE 2018 Digilent will be sponsoring MIPS FPGA workshops. The workshops are based upon the award winning award winning “MIPSfpga” teaching materials and reflects how to use interrupts and performance counters, extends and how to then go inside to look at and modify cache memory and pipeline operations. The course includes materials that allows you to give your students genuine insight into the state-of-the-art in RISC processors.
The second workshop will be held at Room 355 A, Convention Centre, Salt Palace Convention Centre, on June 24, 2018, Sunday at 9am – 12/noon. To register for this one please visit the website. This workshop will be run by Dr. Sarah Harris, who co-authored the popular textbook Digital Design and Computer Architecture, now in its second edition. She led the development of the teaching materials for the MIPS Academic Community (MAC) MIPSfpga program.
To quote Assistant Professor Nachiket Kapre’s from Nanyang Technology University in Singapore thoughts on the course:
“At Nanyang Technology University, Singapore, we used MIPSfpga as part of a graduate-level class project. The students adopted the MIPS RTL and set out to make changes to it to support message-passing between a cluster of cores. We selected MIPS to support our course because we wanted the processor to be in VHDL/Verilog, a language familiar to the students already. The code was modular, easy to understand, and well-documented, and the feedback from students was very positive. We were able to take the class project and package it into an FPGA 2017 conference short paper, a noteworthy outcome for the students beyond simply fulfilling class requirements.”