With the intense tune of Eye of the Tiger playing in the background, it is time to for this showdown to begin. In the left corner we have Verilog. Born in 1984, it didn’t make it to the big scene until 1995. In the right corner we have VHDL, the language created by the US Department of Defense in the 1980’s.
Many people have different opinions on which language is better, but it really comes down to which language you prefer. I should also mention that there is of course System Verilog, but it is very closely related to Verilog so we’ll just leave that for another day. Let’s take a look at these languages and see what the differences are.
VHDL stands for VHSIC Hardware Description Language and VHSIC stands for Very High Speed Integrated Circuit. So on the whole VHDL actually stands for Very High Speed Integrated Circuit Hardware Description Language. Now, that’s a mouthful if I ever saw one! One of the key features of VHDL is that it is a strongly typed language, which means that each data type (integer, character, or etc.) has been predefined by the language itself. All values or variables defined in this language must be described by one of the data types.
VHDL is more verbose than Verilog and it is also has a non-C like syntax. With VHDL, you have a higher chance of writing more lines of code. VHDL can also just seem more natural to use at times. When you’re coding a program with VHDL, it can seem to flow better. But maybe that’s just my personal opinion.
In Verilog, the language is more compact, as the Verilog language is more of a hardware modeling language. You will end up typing few lines of code and it draws similarities to the C language. Verilog has a better grasp on hardware modeling, but has a lower level of programming constructs. Verilog is not as verbose as VHDL so that’s why it’s more compact. All in all, Verilog is pretty different from VHDL. There are some similarities, but they are overshadowed by their differences.
Looking at this example code, we can compare at the how a MUX can be programmed through VHDL and Verilog.
The layout of these programs are very similar; you can reasonably follow what each version of the code is doing. The VHDL version is longer then the Verilog, but it can be understood better.
The last match of this competition is something that can’t be decided easily… it’s the personal preference challenge. This rides on the readers. Weigh in on why you like each programming language, and which one you prefer the most. This is a good opportunity to share some insight on to what beginners should look out for when starting to pick up VHDL or Verilog. If you want to see either language in action, check out some of the learn projects we have on VHDL and Verilog!
Also check out some of our popular projects that use each language. Kaitlyn, a longtime supporter of Verilog details on Instructables some of the awesome things you can do with this powerful tool.
This Pmod can then be used for a variety of applications…some even battle-related.
Check out more on the PmodJSTK powered Jouster here!